A conventional method for manufacturing a semiconductor device will be discussed with reference to the attached drawings.
FIGS. 1a to 1d are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
As shown in FIG. 1a, active regions and field regions are defined on a P-type semiconductor substrate 1. A field oxide layer 2 is formed on the field regions. Subsequently, a first oxide layer, a polysilicon layer and a second oxide layer are successively formed on the entire surface. Utilizing a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are patterned to form a gate oxide layer 3, a gate electrode 4, and a gate cap insulating layer 5. P-type impurity ions are implanted at a tilt angle of 7.degree.-20.degree. into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming first halo regions 6.
Referring to FIG. 1b, P-type impurity ions are implanted at a tilt angle of 30.degree.-60.degree. into the substrate 1 at both sides of the gate electrode 4, so as to form second halo regions 7. In this case, the second halo regions 7 extend further underneath the gate electrode 4 than the first halo regions 6, and have a more shallow depth than the first halo regions 6.
Referring to FIG. 1c, lightly-doped N-type impurity ions are implanted into the semiconductor substrate 1 at both sides of the gate electrode 4, thus forming a lightly doped drain (LDD) regions 8.
Referring to FIG. 1d, utilizing a chemical vapor deposition (CVD) method, an oxide layer is formed on the entire surface and then subjected to etch-back, thus forming insulating sidewalls 9 on the both sides of the gate electrode 4. With the gate electrode 4 and the gate insulating sidewalls 9 serving as masks, highly-doped N-type impurity ions are implanted into the semiconductor substrate 1. This produces source and drain regions 10 in the P-type conductivity-type substrate 1 on both sides of the insulating sidewalls 9. In this case, the depth of the first halo regions 6 is similar to that of the source and drain regions 10, and the depth of the second halo regions 7 is similar to that of the LDD regions 8, thereby improving short channel effects. Thus, the conventional manufacturing of a semiconductor device is completed.
Such a conventional method for manufacturing a semiconductor device has problems.
Ion implantation processes are performed twice to form the different halo regions. The halo regions 6 improve the breakdown voltage characteristics and the halo regions 7 improve short channel effects and adjust the threshold voltage. Consequently, the first and second halo regions overlap each other.
As channel lengths get shortened in highly integrated devices, increasingly high concentrations in the first halo region 6 are required to adjust a breakdown voltage. Consequently, the portions where the first and second halo regions overlap have an even higher doping concentration. As a result, it is hard to adjust threshold voltage using the portions having an overlap-increased, high doping concentration, which causes difficulties in carrying out a successful ion implantation process.